1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and more particularly, to a voltage level comparison circuit, a voltage adjustment circuit using the voltage level comparison circuit, and a semiconductor memory apparatus using the same.
2. Related Art
In general, a semiconductor memory apparatus drops/reduces an external voltage and generates a voltage having a desired level. Here, a circuit that drops the external voltage and generates a stable voltage is commonly called a voltage regulator or a voltage adjustment circuit. Here, the voltage adjustment circuit has been widely used as an internal voltage generation circuit that generates an internal voltage.
FIG. 1 is a schematic diagram of a conventional voltage adjustment circuit of a semiconductor memory apparatus. In FIG. 1, a voltage adjustment circuit 1 includes a comparison unit 10 and a voltage generating unit 20.
The comparison unit 10 compares levels of a reference voltage Vref and an output voltage V_out, and generates a detection signal ‘det’. The comparison unit 10 includes first to fourth transistors P1, P2, N1, and N2. The first transistor P1 is supplied with an external voltage VDD through a source terminal thereof, and supplies a voltage to a first node (node A) that is connected to a drain terminal thereof. The second transistor P2 is supplied with the external voltage VDD through a source terminal thereof, and supplies a voltage to a second node (node B) that is connected to a drain terminal thereof. In the third transistor N1, the output voltage V_out is supplied to a gate terminal thereof, a ground terminal VSS is connected to a source terminal thereof, and the first node (node A) is connected to a drain terminal thereof. In the fourth transistor N2, the reference voltage Vref is supplied to a gate terminal thereof, the ground terminal VSS is connected to a source terminal thereof, and the second node (node A) is connected to a drain terminal thereof.
Here, the detection signal ‘det’ is output from the second node (node A). In addition, the voltage generating unit 20 drives an external voltage VDD according to a potential level of the detection signal ‘det’ and generates the output voltage V_out. The voltage generating unit 20 includes a fifth transistor P3, a resistor element R1, and a capacitor C1. In the fifth transistor P3, the detection signal ‘det’ is supplied to a gate terminal thereof, the external voltage VDD is supplied to a source terminal thereof, and the output voltage V_out is output from a drain terminal thereof. The resistor element R1 and the capacitor C1 are connected in parallel and are connected between the drain terminal of the fifth transistor P3 and the ground terminal VSS. Here, the resistor element R1 and the capacitor C1 that are connected in parallel function as a filter that directs noise of the output voltage V_out to the ground terminal VSS.
In the voltage adjustment circuit 1, if the noise is generated in the external voltage VDD, then the noise is also generated in the output voltage V_out. Specifically, a potential level of the second node (node B), i.e., a potential level of the detection signal ‘det’, is generated by supplying the external voltage VDD to the second node (node B) when the second transistor P2 is turned ON. Thus, the noise of the external voltage VDD is output as the detection signal ‘det’ without being removed. Here, the detection signal ‘det’ that includes the noise is supplied to the gate terminal of the fifth transistor P3 but does not fix a turned-ON degree of the fifth transistor P3. Accordingly, the output voltage V_out that is output from the fifth transistor P3 also includes the noise.